NOTE: This list comes directly from the defines in the ath5k driver. It is used for various debugging and reverse engineering tools and conversion scripts as well as for public reference. Please add any information you have about these registers and add them if you find out the meaning of new registers! Take care, however that you don't violate any NDAs and don't include information from illegal sources!
- ADDRESS: is the register address
- NAME: is the name of the #define as used in the current ath5k/regs.h
- CHIPS: is a comma separated list of chipsets this information applies to. if empty it means "all" chipsets, 5212+ means for 5212 upwards
- NOTES: Notes about the usage of this register
| ADDRESS | NAME (#define) | CHIPS | NOTES |
| 0x0000 | AR5K_NOQCU_TXDP0 | 5210 | Queue 0 - data |
| 0x0004 | AR5K_NOQCU_TXDP1 | 5210 | Queue 1 - beacons |
| 0x0008 | AR5K_CR | Mac Control Register | |
| 0x000c | AR5K_RXDP | RX Descriptor Pointer register | |
| 0x0014 | AR5K_CFG | Configuration and status register | |
| 0x0024 | AR5K_IER | Interrupt enable register | |
| 0x0028 | AR5K_BCR | 5210 | Beacon Control Register |
| 0x0028 | AR5K_RTSD0 | 5211 | first RTS duration register |
| 0x002c | AR5K_BSR | 5210 | Beacon status register |
| 0x002c | AR5K_RTSD1 | 5211 | Second RTS duration register |
| 0x0030 | AR5K_TXCFG | Transmit configuration register | |
| 0x0034 | AR5K_RXCFG | Receive configuration register | |
| 0x0038 | AR5K_RXJLA | 5211 | ? Receive jumbo descriptor last address register |
| 0x0040 | AR5K_MIBC | MIB control register | |
| 0x0044 | AR5K_TOPS | Timeout prescale register | |
| 0x0048 | AR5K_RXNOFRM | Receive timeout register (no frame received) | |
| 0x004c | AR5K_TXNOFRM | Transmit timeout register (no frame sent) | |
| 0x0050 | AR5K_RPGTO | Receive frame gap timeout register | |
| 0x0054 | AR5K_RFCNT | Receive frame count limit register | |
| 0x0058 | AR5K_MISC | Misc settings register | |
| 0x005c | AR5K_QCUDCU_CLKGT | 5311 | QCU/DCU clock gating register |
| 0x001c | AR5K_ISR | 5210 | Interrupt Status Registers |
| 0x0080 | AR5K_PISR | 5211+ | Primary Interrupt Status Register |
| 0x0084 | AR5K_SISR0 | 5211+ | Secondary Interrupt Status Register |
| 0x0088 | AR5K_SISR1 | 5211+ | Secondary Interrupt Status Register |
| 0x008c | AR5K_SISR2 | 5211+ | Secondary Interrupt Status Register |
| 0x0090 | AR5K_SISR3 | 5211+ | Secondary Interrupt Status Register |
| 0x0094 | AR5K_SISR4 | 5211+ | Secondary Interrupt Status Register |
| 0x00c0 | AR5K_RAC_PISR | 5211+ | Read and clear PISR |
| 0x00c4 | AR5K_RAC_SISR0 | 5211+ | Read and clear SISR0 |
| 0x00c8 | AR5K_RAC_SISR1 | 5211+ | Read and clear SISR1 |
| 0x00cc | AR5K_RAC_SISR2 | 5211+ | Read and clear SISR2 |
| 0x00d0 | AR5K_RAC_SISR3 | 5211+ | Read and clear SISR3 |
| 0x00d4 | AR5K_RAC_SISR4 | 5211+ | Read and clear SISR4 |
| 0x0020 | AR5K_IMR | 5210 | Interrupt Mask Registers |
| 0x00a0 | AR5K_PIMR | 5211+ | Interrupt Mask Registers |
| 0x00a4 | AR5K_SIMR0 | 5211+ | Secondary interrupt mask registers |
| 0x00a8 | AR5K_SIMR1 | 5211+ | Secondary interrupt mask registers |
| 0x00ac | AR5K_SIMR2 | 5211+ | Secondary interrupt mask registers |
| 0x00b0 | AR5K_SIMR3 | 5211+ | Secondary interrupt mask registers |
| 0x00b4 | AR5K_SIMR4 | 5211+ | Secondary interrupt mask registers |
| 0x0400 | AR5K_DCM_ADDR | 5212+ | ? Decompression mask address |
| 0x0404 | AR5K_DCM_DATA | 5212+ | ? Decompression mask data |
| 0x0420 | AR5K_DCCFG | 5212+ | Decompression configuration registers |
| 0x0600 | AR5K_CCFG | 5212+ | Decompression configuration registers |
| 0x0604 | AR5K_CCFG_CUP | 5212+ | Decompression configuration registers |
| 0x0610 | AR5K_CPC0 | 5212+ | Compression performance counter 0 |
| 0x0614 | AR5K_CPC1 | 5212+ | Compression performance counter 1 |
| 0x0618 | AR5K_CPC2 | 5212+ | Compression performance counter 2 |
| 0x061c | AR5K_CPC3 | 5212+ | Compression performance counter 3 |
| 0x0620 | AR5K_CPCORN | 5212+ | ? Compression performance overrun |
| 0x0800-0x082c | AR5K_QUEUE_TXDP | 5211+ | QCU TXDP (RANGE) |
| 0x0840 | AR5K_QCU_TXE | 5211+ | QCU Transmit enable register |
| 0x0880 | AR5K_QCU_TXD | 5211+ | QCU Transmit disable register |
| 0x08c0-0x08ec | AR5K_QUEUE_CBRCFG | 5211+ | QCU Constant Bit Rate configuration registers (RANGE) |
| 0x0900-0x092c | AR5K_QUEUE_RDYTIMECFG | 5211+ | QCU Ready time configuration registers (RANGE) |
| 0x0940 | AR5K_QCU_ONESHOTARM_SET | 5211+ | ? QCU one shot arm set registers |
| 0x0980 | AR5K_QCU_ONESHOTARM_CLEAR | 5211+ | QCU one shot arm clear registers |
| 0x09c0-0x09ec | AR5K_QUEUE_MISC | 5211+ | QCU misc registers (RANGE) |
| 0x0a00-0x0a2c | AR5K_QUEUE_STATUS | 5211+ | QCU status registers (RANGE) |
| 0x0a40 | AR5K_QCU_RDYTIMESHDN | 5211+ | QCU ready time shutdown register |
| 0x0b00 | AR5K_QCU_CBB_SELECT | 5212+ | QCU compression buffer base registers |
| 0x0b04 | AR5K_QCU_CBB_ADDR | 5212+ | QCU compression buffer base registers |
| 0x0b08 | AR5K_QCU_CBCFG | 5212+ | QCU compression buffer configuration register |
| 0x1000-0x102c | AR5K_QUEUE_QCUMASK | 5211+ | DCU QCU mask registers (RANGE) |
| 0x1040-0x106c | AR5K_QUEUE_DFS_LOCAL_IFS | 5211+ | DCU local Inter Frame Space settings register (RANGE) |
| 0x1080-0x10ac | AR5K_QUEUE_DFS_RETRY_LIMIT | 5211+ | DCU retry limit registers (RANGE) |
| 0x10c0-0x10ec | AR5K_QUEUE_DFS_CHANNEL_TIME | 5211+ | DCU channel time registers (RANGE) |
| 0x1100-0x112c | AR5K_QUEUE_DFS_MISC | 5211+ | DCU misc registers (RANGE) |
| 0x1140-0x116c | AR5K_QUEUE_DFS_SEQNUM | 5211+ | DCU frame sequence number registers (RANGE) |
| 0x1030 | AR5K_DCU_GBL_IFS_SIFS | 5211+ | DCU global IFS SIFS registers |
| 0x1070 | AR5K_DCU_GBL_IFS_SLOT | 5211+ | DCU global IFS slot interval registers |
| 0x10b0 | AR5K_DCU_GBL_IFS_EIFS | 5211+ | DCU global IFS EIFS registers |
| 0x10f0 | AR5K_DCU_GBL_IFS_MISC | 5211+ | DCU global IFS misc registers |
| 0x1230 | AR5K_DCU_FP | 5211+ | DCU frame prefetch control register |
| 0x1270 | AR5K_DCU_TXP | 5211+ | DCU transmit pause control/status register |
| 0x1038 | AR5K_DCU_TX_FILTER | 5211+ | DCU transmit filter register |
| 0x143c | AR5K_DCU_TX_FILTER_CLR | 5211+ | DCU clear transmit filter register |
| 0x147c | AR5K_DCU_TX_FILTER_SET | 5211+ | DCU set transmit filter register |
| 0x4000 | AR5K_RESET_CTL | Reset control register | |
| 0x4004 | AR5K_SLEEP_CTL | Sleep control register | |
| 0x4008 | AR5K_INTPEND | Interrupt pending register | |
| 0x400c | AR5K_SFR | Sleep force register | |
| 0x4010 | AR5K_PCICFG | PCI configuration register | |
| 0x4014 | AR5K_GPIOCR | General Purpose Input/Output" (GPIO) control register | |
| 0x4018 | AR5K_GPIODO | "General Purpose Input/Output" (GPIO) data output register | |
| 0x401c | AR5K_GPIODI | "General Purpose Input/Output" (GPIO) data input register | |
| 0x4020 | AR5K_SREV | Silicon revision register | |
| 0x6000 | AR5K_EEPROM_BASE | EEPROM base address | |
| 0x6004 | AR5K_EEPROM_DATA_5211 | 5211+ | EEPROM data register |
| 0x6800 | AR5K_EEPROM_DATA_5210 | 5210 | EEPROM data register |
| 0x6008 | AR5K_EEPROM_CMD | EEPROM command register | |
| 0x6c00 | AR5K_EEPROM_STAT_5210 | 5210 | EEPROM status register |
| 0x600c | AR5K_EEPROM_STAT_5211 | 5211+ | EEPROM status register |
| 0x6010 | AR5K_EEPROM_CFG | ? EEPROM config register | |
| 0x8000 | AR5K_STA_ID0 | First station id register (MAC address in lower 32 bits) | |
| 0x8004 | AR5K_STA_ID1 | Second station id register (MAC address in upper 16 bits) | |
| 0x8008 | AR5K_BSS_ID0 | First BSSID register (MAC address, lower 32bits) | |
| 0x800c | AR5K_BSS_ID1 | Second BSSID register (MAC address in upper 16 bits) | |
| 0x8010 | AR5K_SLOT_TIME | Backoff slot time register | |
| 0x8014 | AR5K_TIME_OUT | ACK/CTS timeout register | |
| 0x8018 | AR5K_RSSI_THR | RSSI threshold register | |
| 0x801c | AR5K_NODCU_RETRY_LMT | 5210 | Retry limit register for 5210 (no QCU/DCU so it's done in PCU) |
| 0x8020 | AR5K_USEC_5210 | 5210 | Transmit latency register |
| 0x801c | AR5K_USEC_5211 | 5211+ | Transmit latency register |
| 0x8024 | AR5K_BEACON_5210 | 5210 | PCU beacon control register |
| 0x8020 | AR5K_BEACON_5211 | 5211+ | PCU beacon control register |
| 0x8028 | AR5K_CFP_PERIOD_5210 | 5210 | CFP period register |
| 0x8024 | AR5K_CFP_PERIOD_5211 | 5211+ | CFP period register |
| 0x802c | AR5K_TIMER0_5210 | 5210 | Next beacon time register |
| 0x8028 | AR5K_TIMER0_5211 | 5211+ | Next beacon time register |
| 0x8030 | AR5K_TIMER1_5210 | 5210 | Next DMA beacon alert register |
| 0x802c | AR5K_TIMER1_5211 | 5211+ | Next DMA beacon alert register |
| 0x8034 | AR5K_TIMER2_5210 | 5210 | Next software beacon alert register |
| 0x8030 | AR5K_TIMER2_5211 | 5211+ | Next software beacon alert register |
| 0x8038 | AR5K_TIMER3_5210 | 5210 | Next ATIM window time register |
| 0x8034 | AR5K_TIMER3_5211 | 5211+ | Next ATIM window time register |
| 0x8040 | AR5K_IFS0 | 5210 | First inter frame spacing register (IFS) |
| 0x8044 | AR5K_IFS1 | 5210 | Second inter frame spacing register (IFS) |
| 0x8048 | AR5K_CFP_DUR_5210 | 5210 | CFP duration register |
| 0x8038 | AR5K_CFP_DUR_5211 | 5211+ | CFP duration register |
| 0x804c | AR5K_RX_FILTER_5210 | 5210 | Receive filter register |
| 0x803c | AR5K_RX_FILTER_5211 | 5211+ | Receive filter register |
| 0x8050 | AR5K_MCAST_FILTER0_5210 | 5210 | Multicast filter register (lower 32 bits) |
| 0x8040 | AR5K_MCAST_FILTER0_5211 | 5211+ | Multicast filter register (lower 32 bits) |
| 0x8054 | AR5K_MCAST_FILTER1_5210 | 5210 | Multicast filter register (higher 16 bits) |
| 0x8044 | AR5K_MCAST_FILTER1_5211 | 5211+ | Multicast filter register (higher 16 bits) |
| 0x8058 | AR5K_TX_MASK0 | 5210 | Transmit mask register (lower 32 bits) |
| 0x805c | AR5K_TX_MASK1 | 5210 | Transmit mask register (higher 16 bits) |
| 0x8060 | AR5K_CLR_TMASK | 5210 | Clear transmit mask |
| 0x8064 | AR5K_TRIG_LVL | 5210 | Trigger level register (before transmission) |
| 0x8068 | AR5K_DIAG_SW_5210 | 5210 | PCU control register |
| 0x8048 | AR5K_DIAG_SW_5211 | 5211+ | PCU control register |
| 0x806c | AR5K_TSF_L32_5210 | 5210 | TSF (clock) register (lower 32 bits) |
| 0x804c | AR5K_TSF_L32_5211 | 5211+ | TSF (clock) register (lower 32 bits) |
| 0x8070 | AR5K_TSF_U32_5210 | 5210 | TSF (clock) register (higher 32 bits) |
| 0x8050 | AR5K_TSF_U32_5211 | 5211+ | TSF (clock) register (higher 32 bits) |
| 0x8080 | AR5K_LAST_TSTP | Last beacon timestamp register | |
| 0x8054 | AR5K_ADDAC_TEST | 5211+ | ADDAC test register |
| 0x8058 | AR5K_DEFAULT_ANTENNA | 5211+ | Default antenna register |
| 0x8084 | AR5K_RETRY_CNT | 5210 | Retry count register |
| 0x8088 | AR5K_BACKOFF | 5210 | Back-off status register |
| 0x808c | AR5K_NAV_5210 | 5210 | NAV register (current) |
| 0x8084 | AR5K_NAV_5211 | 5211+ | NAV register (current) |
| 0x8090 | AR5K_RTS_OK_5210 | 5210 | RTS success register |
| 0x8088 | AR5K_RTS_OK_5211 | 5211+ | RTS success register |
| 0x8094 | AR5K_RTS_FAIL_5210 | 5210 | RTS failure register |
| 0x808c | AR5K_RTS_FAIL_5211 | 5211+ | RTS failure register |
| 0x8098 | AR5K_ACK_FAIL_5210 | 5210 | ACK failure register |
| 0x8090 | AR5K_ACK_FAIL_5211 | 5211+ | ACK failure register |
| 0x809c | AR5K_FCS_FAIL_5210 | 5210 | FCS failure register |
| 0x8094 | AR5K_FCS_FAIL_5211 | 5211+ | FCS failure register |
| 0x80a0 | AR5K_BEACON_CNT_5210 | 5210 | Beacon count register |
| 0x8098 | AR5K_BEACON_CNT_5211 | 5211+ | Beacon count register |
| 0x80c0 | AR5K_XRMODE | 5212 | XR (eXtended Range) mode register |
| 0x80c4 | AR5K_XRDELAY | 5212 | XR delay register |
| 0x80c8 | AR5K_XRTIMEOUT | 5212 | XR timeout register |
| 0x80cc | AR5K_XRCHIRP | 5212 | XR chirp register |
| 0x80d0 | AR5K_XRSTOMP | 5212 | XR stomp register |
| 0x80d4 | AR5K_SLEEP0 | 5212 | First enhanced sleep register |
| 0x80d8 | AR5K_SLEEP1 | 5212 | Second enhanced sleep register |
| 0x80dc | AR5K_SLEEP2 | 5212 | Third enhanced sleep register |
| 0x80e0 | AR5K_BSS_IDM0 | 5212 | BSSID mask registers |
| 0x80e4 | AR5K_BSS_IDM1 | 5212 | BSSID mask registers |
| 0x80e8 | AR5K_TXPC | 5212 | TX power control (TPC) register |
| 0x80ec | AR5K_PROFCNT_TX | 5212 | Profile count registers |
| 0x80f0 | AR5K_PROFCNT_RX | 5212 | Profile count registers |
| 0x80f4 | AR5K_PROFCNT_RXCLR | 5212 | Profile count registers |
| 0x80f8 | AR5K_PROFCNT_CYCLE | 5212 | Profile count registers |
| 0x8104 | AR5K_TSF_PARM | 5212 | TSF parameter register |
| 0x810c | AR5K_PHY_ERR_FIL | 5212 | PHY error filter register |
| 0x8700-0x877c | AR5K_RATE_DUR | 5212 | Rate duration register |
| 0x9000 | AR5K_KEYTABLE_0_5210 | 5210 | Key table (WEP) register |
| 0x8800-0x9800 | AR5K_KEYTABLE_0_5211 | 5211+ | Key table (WEP) register |
| 0x9800 | AR5K_PHY | PHY unknown register | |
| 0x9804 | AR5K_PHY_TURBO | PHY frame control register [5110] /turbo mode register [5111+] | |
| 0x9808 | AR5K_PHY_AGC | PHY agility command register | |
| 0x9814 | AR5K_PHY_TIMING_3 | 5112+ | PHY timing register |
| 0x9818 | AR5K_PHY_CHIP_ID | PHY chip revision register | |
| 0x981c | AR5K_PHY_ACT | PHY activation register | |
| 0x9858 | AR5K_PHY_SIG | PHY signal register | |
| 0x985c | AR5K_PHY_AGCCOARSE | PHY coarse agility control register | |
| 0x9860 | AR5K_PHY_AGCCTL | PHY agility control register | |
| 0x9864 | AR5K_PHY_NF | PHY noise floor status register | |
| 0x9868 | AR5K_PHY_ADCSAT | 5110 | PHY ADC saturation register |
| 0x9870 | AR5K_PHY_SCR | 5112+ | PHY sleep registers |
| 0x9874 | AR5K_PHY_SLMT | 5112+ | PHY sleep registers |
| 0x9878 | AR5K_PHY_SCAL | 5112+ | PHY sleep registers |
| 0x987c | AR5K_PHY_PLL | PHY PLL (Phase Locked Loop) control register | |
| 0x989c | AR5K_RF_BUFFER | RF Buffer register | |
| 0x98c0 | AR5K_RF_BUFFER_CONTROL_0 | RF Buffer register | |
| 0x98c4 | AR5K_RF_BUFFER_CONTROL_1 | RF Buffer register | |
| 0x98cc | AR5K_RF_BUFFER_CONTROL_2 | RF Buffer register | |
| 0x98d0 | AR5K_RF_BUFFER_CONTROL_3 | RF Buffer register | |
| 0x98d4 | AR5K_RF_BUFFER_CONTROL_4 | RF Buffer register | |
| 0x98d8 | AR5K_RF_BUFFER_CONTROL_5 | RF Buffer register | |
| 0x98dc | AR5K_RF_BUFFER_CONTROL_6 | RF Buffer register | |
| 0x98d4 | AR5K_PHY_RFSTG | 5210 | PHY RF stage register |
| 0x9914 | AR5K_PHY_RX_DELAY | 5111+ | PHY receiver delay register |
| 0x9920 | AR5K_PHY_IQ | 5111+ | PHY timing I(nphase) Q(uadrature) control register |
| 0x9930 | AR5K_PHY_PAPD_PROBE | 5111+ | ? PHY PAPD probe register |
| 0x9934 | AR5K_PHY_TXPOWER_RATE1 | 5112+ | PHY TX rate power registers |
| 0x9938 | AR5K_PHY_TXPOWER_RATE2 | 5112+ | PHY TX rate power registers |
| 0x993c | AR5K_PHY_TXPOWER_RATE_MAX | 5112+ | PHY TX rate power registers |
| 0xa234 | AR5K_PHY_TXPOWER_RATE3 | 5112+ | PHY TX rate power registers |
| 0xa238 | AR5K_PHY_TXPOWER_RATE4 | 5112+ | PHY TX rate power registers |
| 0x9804 | AR5K_PHY_FRAME_CTL_5210 | 5210 | PHY frame control register |
| 0x9944 | AR5K_PHY_FRAME_CTL_5211 | 5111+ | PHY frame control register |
| 0x9954 | AR5K_PHY_RADAR | 5111+ | PHY radar detection register |
| 0x9960 | AR5K_PHY_ANT_SWITCH_TABLE_0 | 5110 | PHY antenna switch table registers |
| 0x9964 | AR5K_PHY_ANT_SWITCH_TABLE_1 | 5110 | PHY antenna switch table registers |
| 0x99f0 | AR5K_PHY_SCLOCK | 5112+ | PHY clock sleep registers |
| 0x99f4 | AR5K_PHY_SDELAY | 5112+ | PHY clock sleep registers |
| 0x99f8 | AR5K_PHY_SPENDING | 5112+ | PHY clock sleep registers |
| 0x9a00-0x9afc | AR5K_RF_GAIN | 5110,5111 | RF Amplifier Gain table |
| 0x9b00-0x9bfc | AR5K_BB_GAIN | 5110,5111 | BaseBand? Amplifier Gain table |
| 0x9c10 | AR5K_PHY_IQRES_CAL_PWR_I | 5111+ | PHY timing IQ calibration result register: I (Inphase) power value |
| 0x9c14 | AR5K_PHY_IQRES_CAL_PWR_Q | 5111+ | PHY timing IQ calibration result register: Q (Quadrature) power value |
| 0x9c18 | AR5K_PHY_IQRES_CAL_CORR | 5111+ | PHY timing IQ calibration result register: I/Q Correlation |
| 0x9c1c | AR5K_PHY_CURRENT_RSSI | 5111+ | PHY current RSSI register |
| 0xa180-0xa1fc | AR5K_PHY_PCDAC_TXPOWER | PHY PCDAC TX power table | |
| 0xa200 | AR5K_PHY_MODE | 5111+ | PHY mode register |
| 0xa204 | AR5K_PHY_CCKTXCTL | 5111+ | ? PHY CCK transmit control register |
| 0xa20c | AR5K_PHY_GAIN_2GHZ | 5111+ | PHY 2GHz gain register |
| 0x4000-0x5000 | (PCI_TIMING) | 5212+ | PCI Timing (RANGE) |
